http://www.geek.com/procspec/features/revx86/index.htm

I've been reading this and it's really interesting!
Warning, not for computer non-freaks.

Or you could simply get a sparc instead...

Oh really.....
I wonder how getting a sparc will improve x86 performence...
Come on man, be a little bit serious I've read that entire article, and i think his ideas are simply groundbreaking.. Yeah you can add all those little jokes like "or you could simply get a spark", but come on...

Actually I was serious... For nice instruction sets you should look at some RISC processor instead. But as you say we are stuck with x86 so that won't help us. If this proposal really works in practice it would be great, but for some reason I'm sceptic.

For example: He didn't mention anything about how pipelining would be affected. Only said thet he wanted it implemented in the decode stage... then nothing about how it affects the stages where data is read and stored in the registers.

Secondly I have no idea if there are any wires in the processor from SSE registers to GP reg at all... My guess is that there is not, and then it would be sort of impossible. Would also explain why there is no such instructions yet Maybe google can help me find out more... I'll be back.

That's not true. He DID mention things about pipelining and said it will NOT be affected, you didn't read properly. He said that for more info on that you can email him to get details how that can be done.

Well, such wires can be easily added by the manufacturer don't you think?.. I don't see a problem here at all.

I can't help you find out more, All is on that article..

This sounds similar to what Intel is doing with hyperthreading in using unused registers to do work faster. It would be great to have processors have a real speed boost coming from something other than just another clockspeed upgrade.

It's quite different...but there is a resamblance.

Well. If the registers are located too far apart on the chip it would introduce a long delay which would force you to go down in clockspeed. I was looking for some picture of the layout of the p4, but haven't found any yet...

Just send him an email to get the info if you want total proof that his modifications will not degrade any quality whatsoever .

I just did. I hope he takes the time to answer...

Hmm, I don't think one can make much more out of x86 architecture. It never was good to begin with. Let's put our hopes on the success of IA-64 architecture. EPIC (Explicitly Parallel Instruction Computing) of IA-64 is far more a revolutionary idea than adding multimedia extensions. I never believed in extra circuitry in CISC processors to do out-of-order processing (and decide which ones are independent), branch prediction, etc. They were too gross to be put into hardware. Now all such complications of instruction ordering, etc. are assigned to compilers. Processor does not have to guess anything, therefore it achieves the maximum parallelism. Because compiler orders the instructions to make most of all the circuitry in the processor. It is VLIW (very large instruction word) pushed to the extreme (by additional instruction hinting). And IA-64's predication is a very efficient way to handle branches. Given those I don't care a fig for the future of x86 (which is by my opinion already dead). And multimedia extensions in my opinion, is not a graceful addition to the instruction set. You can produce a separate multimedia processor for that purpose.

Now given that, though I usually liked AMD because they produced cheaper and faster CPUs., I hope they utterly fail in their x86-64 extensions . Because we should not go on using 10 years old technology. AMD has no options except for x86-64's success because Intel spent billions in R&D of IA-64 whereas AMD has no experience in IA-64. However if Intel does not come up with cheaper 64 bit alternatives to huge-cache Itaniums, AMD might get very popular. Which would mean we'd go on with this x86 crap for another decade. I once thought Intel is evil in the sense that they form peaceful coexistence with Microsoft and support ideas like palladium. But still they want to produce better technology (unlike Microsoft and possibly AMD) and therefore aim for doing some good for community. Yet all MS and AMD cares for is their revenue.
I don't think I'd ever buy AMD again.

Alp

....
The thing here is that people are trying to improve what is too difficult, so that it will be less difficult, and have better performence, untill Intel's new processors (built from scratch, not x86) will take over the market in 2005/6/7 tops.
I see NO reason not to improve the performence and ease of the most popular system in the world, makes no sense. EVERYbody will gain from it. Programmers especially and end users who will get better performence.

And it's not a 10 year old technology, it's a 22 year old technology.

Well, who's going to implement it? You? Intel's last x86 architecture is going to come around 2005, as far as I know. That means its instruction set is definitely settled. This guy mentions about new registers and instructions. Why would we spend time with extending x86 when we can pass to the real thing? Loss of engineering time.

BTW do you know how long it takes to design a processor?

...
Yes! -I- will implement it! Alone, and i have all the knowlage in the world.
Yes, this guy mentions new register and instructions. Why spend time? Well, first it won't take 3 years to do, i don't think it's THAT super complicated (i may be wrong, be i highly doubt it). "We" wouldn't spend any time with extending x86, they will, he was giving suggestions, as an experienced programmer he knows what he would like to have been different, and thought of a great way that can dramatically improve programming difficulties and enhance the performence of almost all applications running on a x86 machine. Loss of engineering time? Really, HOW? As you said, their last x86 implementation will be around 2005, they can add/modify things to work this way, i'm pretty sure. They have well enough engineering resources...

"BTW do you know how long it takes to design a processor?"
Oh no i don't, please enlighten me wise one... I'm so sure YOU know..
It takes a long time. I'd estimate it will take intel around 12 years to complete their new processor, which will probably be availible by 2007 or maybe even 6.

Do you think you know so much? You said x86 is a 10 year old technology, when in fact the first x86 implementation was introduced in 1978.
I don't try to sound smart, i just share my opinions. You like to sound smart.

Now that's becoming ignorant.

Please, calm down, SK1 and Atici. No flamewars over processors on an Audio Coding forum. :-P (Or over anything else, of course...)

OK sorry. Me calmed down.

edited: Sorry, no offtopic flamewars.. But really, i didn't mean to sound like an ass. But he was the one who said "Well, who's going to implement it? You?" yeah now that's mature, and "BTW do you know how long it takes to design a processor?" obviously that's just trying to sound smart... Yeah, sure, i work with intel and know this kind of things, you do too.. Come on.
Anyway sorry, but mommy i'm not the one who started it, HE did it, he was first, he made me do it, and all those idiotic childish excuses

I dunno about you all, but I am going to take in account that Intel's next-gen chips are going to be riddled with DRM garbage when I come to purchasing my next processor.

Maybe I am mistaken, but I thought AMD was the one who gladly implemented palladium technology into their hammer and Intel who rejected the palladium technology.

Correct me if I am wrong.

The author basically descibres additions to the x86 instruction set that make for a complicated way to be able to use more registers.

How exactly is this revolutionary?

Edit: Or worse, 'groundbreaking'?

Both AMD and Intel both embraced Palladium with open arms... They are the biggest supporters of Microsoft's communist software/hardware... :/

"The author basically descibres additions to the x86 instruction set that make for a complicated way to be able to use more registers."

I think it's more complicated using the limited number of registers to achieve good results than using more.
I say ok, what ever, obviously it's easy to find something negative in everything, no matter how positive it is.

But there is nothing positive in it whatsoever!

The author basically reinvents register renaming (done in any modern CPU) in a much worse and incompatible way, and then goes to call it revolutionary.

You know what, i don't think what you say is very true. But i'm not a programmer and with no doubt you know *much* more than i do, so i won't even dare to argue.

Actually, I don't really know much about the latest Processor "garbage".. For me, the MMX and SIMD instructions and the duel pipeline concept of the pentium processor is already very fast.. Eg, it is possible to encode MPEG-1, 320 x 240 pixel, 30 frame persecond, real time on a pentium 200 MHz MMX machine.

From my personal experience when dissemblying x86 compiled codes, the u-v pipeline isn't paired.. As a result, most of the time, the pentium processor is operating only at half capacity.., one instructions at a time when it could execute 2 instructions at a time! Then, there is a terrible habit of programmers to mixed data types, such as int32 with int16 or type char.. which is very-very bad!
Type char and int16 will introduce additional delays when executed.. Only type int32 will fit nicely into the pipeline and be executed once every clock cycle..\

Integer Multiplications and Divisions should be avoided if necessary.. as they take up enormous time to execute.. Instead these could be implemented in a series of simple shift and add operation which is far-far more efficient..

Also all these hype about RISC processors being able to execute faster than CISC processors is all nonsense.. Pure marketing effort... RISC processors required that the codes be written in simplified instructions sets.. In that case, if you properly write similar codes for the Pentium processors, you can still get the same results if not better because of the duel u-v pipeline concept... The Pentium processor is a hibrid RISC-CISC processor..

Then there are additional "complex" instructions which could for example, subtract a block of 8 data of type bytes from another similar block, calculate the abs of each individual subtractions and sum up all 8 results and store in the EAX register in "Just One Clock CYcle".. This is almost equavalent to about 100 instructions executions.. This is the SIMD instructions set.. Better still, you can still pair the 2 instructions together in the u-v pipeline and this will give you an equavalent of 200 instructions..

Actually for a Pentium 90 MHz system, it is possible to execute 160 Million instructions per second if the software is properly optimized! For more information on this, try using the Intel V-Tune Tools.. It is a very powerful tool for software optimization.. It allows you to see, which instructions paired or isn't paired in the u-v pipeline, instructions latency (integer multiplications and divisions), caching optimizations , which functions are computationally intensive and etc-etc..

You have to optimize the codes in assembly language in order to fully realize the full potential of the pentium processor..

wkw

There's a huge discussion about this over on Slashdot... enjoy...

Well I don't intend any flamewar or anything. But I think proposing such an extension is a little bit fruitless. Because it's Intel and AMD who's designing the chips. And Intel already probably taped-out its latest x86 design. Moreover there're lots of other complications with processor production. One can't simply argue in favor of adding new instructions and registers without knowing how intel processor handles things in hardware or how many new transistors are going to be introduced. What will happen to pipelines, etc.? It's a massive design issue. You can't update your cpu in a day. That's why I personally find it fruitless, we have much better alternatives to direct engineering effort into (like IA-64).

Yes it does sound like Intel's Hyper Threading. Unfortuantely, the software has to be optimized in order to take advantage of it, just like MMX, SSE, and SSE2...

After reading this text I recommend the author of this text to employ with following
topics:

- mode of operation of modern CPUs introduced with Pentium Pro / Pentium II / AMD K-6
- mode of operation of CPUs introduced with Transmeta / Pentium 4
- typical problems / constraint in modern CPU design
- building of compilers / code optimization of compilers

Thanks but no, the surprise element is a powerful tool (pfff yeah ..)

ur wrong.

intel refused at first, but at some point for some reason, they agreed.. or forced to agree (??).

but AMD, in order to lick some serious microsoft ass, went away and implemented it.

I have a hard time believing that Intel would be against it since they were the first ones to start off with discriminating their users... Remember their PIII with a unique code that could be used to identify each and everyone on the Internet?